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AVR32768: 32-Bit AVR UC3 C Series Schematic Checklist
Features
* * * * * * * * * * * * Power circuit Reset circuit Clocks and crystal oscillators Analog-to-digital Converter Digital-to-analog Converter USB connection Ethernet MAC interface External bus interface Quadrature decoder CAN interface USB DFU ISP Entry Point JTAG and Nexus debug ports
32-bit Microcontrollers Application Note
1 Introduction
A good hardware design comes from a proper schematic. Because Atmel(R) AVR(R) UC3 C devices have a fair number of pins and functions, the schematic for these devices can be large and quite complex. This application note describes a common checklist which should be used when starting and reviewing the schematics for an UC3 C design.
Rev. 32157A-AVR-12/10
2 Abbreviations
DAC DFU ISP MII Digital-to-analog converter Direct Firmware Upgrade In-System Programming Media Independent Interface Reduced Media Independent Interface Sample and Hold Wake-on-LAN
QDEC Quadrature decoder RMII S/H WOL
3 References
3.1 Device datasheet
The device datasheet contains block diagrams of the peripherals and details about implementing firmware for the device. The datasheet is available on http://www.atmel.com/AVR in the Datasheets section.
3.2 The AVR Software Framework
http://asf.atmel.no/readme.html All pre-loaded firmware source codes are available in the Atmel AVR Software Framework version 2.0 or higher.
3.3 The AT32UC3C-EK Getting Started
http://www.atmel.com/uc3c-ek
3.4 USB DFU boot loader
http://www.atmel.com/AVR
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4 Power circuit
The UC3 C can be used in two different power supply modes. * 3.3V single power supply mode * 5V single power supply mode Two internal voltage regulators, a 3.3V regulator and a 1.8V regulator, supply power to the USB pads and VDDCORE respectively.
4.1 Single 3.3V power supply
Figure 4-1. Single 3.3V power supply example schematic.
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Table 4-1. Single 3.3V power supply checklist.
Signal name Recommended pin connection 3.0V to 3.6V RF EMI inductor Decoupling/filtering capacitor, (1) 100nF to GNDANA Connect to analog ground 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V Decoupling/filtering capacitors, (1)(2) and 470pF (1)(2) 2.2F Connect to digital ground Connect to digital ground Connect to digital ground Description
VDDANA
Analog power supply
GNDANA VDDIO VDDIN_5 VDDIN_33 VDDCORE GNDCORE GNDPLL GNDIO Notes:
Analog ground Powers I/O lines and the flash memory Input voltage for the 1.8V regulator USB I/O power supply Stabilization output for the 1.8V regulator Decoupling/filtering capacitors must be added to ensure regulator stability
1. These values are given only as a typical example 2. Decoupling capacitor should be placed as close as possible to the pin
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4.2 Single 5V power supply
Figure 4-2. Single 5V power supply example schematic.
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Table 4-2. Single 5V power supply checklist (UC3 C).
Signal name Recommended pin connection 4.5V to 5.5V RF EMI inductor Decoupling/filtering capacitor, (1) 100nF to GNDANA Connect to analog ground 4.5V to 5.5V 4.5V to 5.5V Decoupling/filtering capacitors, (1)(2) and 470pF (1)(2) 2.2F Decoupling/filtering capacitors, 2.2F (1)(2) and 470pF (1)(2) Connect to digital ground Connect to digital ground Connect to digital ground Description
VDDANA
Analog power supply
GNDANA VDDIO VDDIN_5 VDDIN_33 VDDCORE GNDCORE GNDPLL GNDIO Notes:
Analog ground Powers I/O lines and the flash memory Input voltage for the 1.8V regulator USB I/O power supply Decoupling/filtering capacitors must be added to ensure regulator stability Stabilization output for the 1.8V regulator Decoupling/filtering capacitors must be added to ensure regulator stability
1. These values are given only as a typical example 2. Decoupling capacitor should be placed as close as possible to the pin
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5 Reset circuit
The reset pin is also used for aWire (see section 14.3 for details). Figure 5-1. Reset circuit example schematic. VDDIO 10 k 100 nF RESET_N
Table 5-1. Reset circuit checklist.
Signal name RESET_N Recommended pin connection Description Can be left unconnected in case The RESET_N pin is a Schmitt input and integrates a permanent pull-up no reset from the system needs to resistor to VDDIO be applied to the product
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6 Clocks and crystal oscillators
There are three clock inputs available: * XIN0 / XOUT0 * XIN1 / XOUT1 * XIN32 / XOUT32 The recommendations below refer to XIN / XOUT, but apply to all the clock inputs.
6.1 External clock source
Figure 6-1. External clock source schematic.
Table 6-1. External clock source checklist.
Signal name XIN XOUT Recommended pin connection Connected to clock output from external clock source Can be left unconnected or used as GPIO Description Up to VDDIO-volt square wave signal up to 50MHz
6.2 Crystal oscillator
Figure 6-2. Crystal oscillator example schematic.
Table 6-2. Crystal oscillator checklist.
Signal name XIN XOUT Notes: Recommended pin connection Biasing capacitor, 22pF Biasing capacitor, 22pF
(1)(2) (1)(2)
Description External crystal between 450kHz and 16MHz
1. These values are given only as a typical example. The capacitance, C, of the biasing capacitors can be computed based on the crystal load capacitance, CL, and the internal capacitance, Ci, of the MCU as follows: C = 2(CL - Ci) The value of CL can be found in the crystal datasheet and the value of Ci can be found in the MCU datasheet 2. Decoupling capacitor should be placed as close as possible to each pin in the signal group, and vias should be avoided
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7 ADC Analog-to-digital converter
The UC3 C analog-to-digital converter (ADC) has a fully differential 8/10/12-bit ADC core with built-in sample and hold. It has multiple reference sources, and 1.5 megasamples per second conversion rate for 12 bit resolution. The ADC connections require some electrical considerations, which are outlined in this section.
7.1 ADC analog Input
The ADC has 16 channels of analog input, ADCINx, which are GPIO multiplexed. To get the best resolution, it is recommended not to use digital features of GPIO pins close to the analog inputs used. The analog input channels require a low enough external source impedance, which depends on whether or not sample-and-hold is used (see Table 7-1). For differential input, ADCIN[0:7] are used for positive input and ADCIN[8:15] are used for negative input. In single-ended mode, all 16 channels can be used as singleended input. Please refer to the UC3 C datasheet for details. Table 7-1. ADC analog inputs.
Signal name Recommended pin connection Maximum input voltage: VVDDANA Maximum external source impedance, * without S/H: 3k * with S/H: 1k Description
ADCINx
Analog input
7.2 ADC voltage reference
The internal analog-to-digital converter in the UC3 C can use different voltage references. Depending on the voltage references needed, the external voltage reference pins should be connected as advised below. 7.2.1 ADC single-ended external reference (ADCREF0/ADCREF1) Two external, single-ended voltage references are available. The maximum voltage values depend on the power supply mode used. Refer to Table 7-2 and Table 7-3, and Figure 7-1 and Figure 7-2. If the single-ended external voltage references are not used, the pins can be left unconnected and tied to internal pull-up through GPIO. Figure 7-1. Single-ended external reference, 3.3V power supply mode.
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Table 7-2. ADC single-ended external voltage reference, 3.3V power supply mode.
Signal name ADCREF0 ADCREF1 Recommended pin connection 1.0V to 2.6V 1.0V to 2.6V Description Single-ended external voltage reference Single-ended external voltage reference
Figure 7-2. Single-ended external reference, 5V power supply mode.
DC/DC converter
1.0 to 3.5 V
ADCREF0
DC/DC converter
ADCREF1
1.0 to 3.5 V
Table 7-3. ADC single-ended external voltage reference, 5V power supply mode.
Signal name ADCREF0 ADCREF1 Recommended pin connection 1.0V to 3.5V 1.0V to 3.5V Description Single-ended external voltage reference Single-ended external voltage reference
7.2.2 ADC differential external reference pins (ADCVREFP/ADCVREFN) In order to use the internal 1V bandgap reference, the ADCVREFP and ADCVREFN pins must be used with decoupling capacitors (see Figure 7-3 and Table 7-5 for typical values). If the internal voltage reference is unused, ADCVREFP and ADCVREFN can be used as differential external voltage reference (see Figure 7-4 and Table 7-5). Figure 7-3. ADCVREFP/ADCVREFN external decoupling for use of internal bandgap reference.
Table 7-4. ADC differential external voltage reference, internal reference used.
Signal name ADCVREFP ADCVREFN Recommended pin connection Positive differential voltage Negative differential voltage Description Differential external voltage reference Differential external voltage reference
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Figure 7-4. Differential external voltage reference.
Table 7-5. ADC differential voltage inputs, internal reference not used.
Signal name ADCVREFP ADCVREFN Recommended pin connection 100nF decoupling capacitor 100nF decoupling capacitor Description Used as decoupling for internal reference voltage Used as decoupling for internal reference voltage
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8 Digital-to-analog converter
The digital-to-analog converter (DAC) can use either an internal or external voltage reference. When using an internal voltage reference, DACREF can be GPIO multiplexed to another function or connected to an internal pull-up.
8.1 DAC connection
Figure 8-1. DAC connection considerations. 1.1V to DC/DC VDDANA-0.3V Power Source converter DACREF
1.1 to VDDANA-0.3 V
1 k
DAC0A
1 k
DAC0B
Table 8-1. Digital-to-analog converter checklist.
Signal name DACREF DAC0A DAC0B Recommended pin connection Reference voltage range: 1.1V - (VDDANA-0.3V) Minimum load impedance: 1k Maximum load capacitance: 100pF Minimum load impedance: 1k Maximum load capacitance: 100pF Description External voltage reference Channel A analog output Channel B analog output
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9 USB connection
9.1 Not used
When the USB interface is not used, DM, DP and VBUS should be connected to ground.
9.2 Device mode, bus-powered connection
Figure 9-1. USB in device mode, bus-powered connection example schematic. VDD 3.3 volt regulator
USB_VBOF
VBUS
VBUS
D-
DM 39 DP 39 USB_ID
D+
ID GND
Table 9-1. USB bus-powered connection checklist.
Signal name USB_VBOF VBUS DM Recommended pin connection Can be left unconnected Directly to connector 39 series resistor Placed as close as possible to DM pin 39 series resistor Placed as close as possible to DP pin Can be used as GPIO if not used Description USB power control pin USB power pin Negative differential data line
DP USB_ID
Positive differential data line USB connector identification pin
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9.3 Device mode, self-powered connection
Figure 9-2. USB in device mode, self-powered connection example schematic. USB_VBOF
VBUS
VBUS
D-
DM 39 DP 39 USB_ID
D+
ID GND
Table 9-2. USB self-powered connection checklist.
Signal name USB_VBOF VBUS DM Recommended pin connection Can be left unconnected Directly to connector 39 series resistor Placed as close as possible to DM pin 39 series resistor Placed as close as possible to DP pin Can be used as GPIO if not used Description USB power control pin USB power pin Negative differential data line
DP USB_ID
Positive differential data line USB connector identification pin
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9.4 Host mode, powered from bus connection
Figure 9-3. USB host-powering connection example schematic.
5.0 volt regulator
USB_VBOF
VBUS
VBUS
D-
DM 39 DP 39 USB_ID
D+
ID GND
Table 9-3. USB host-powering connection checklist.
Signal name USB_VBOF VBUS DM Recommended pin connection GPIO connected to VBUS 5.0V regulator enable signal Directly to connector 39 series resistor Placed as close as possible to DM pin 39 series resistor Placed as close as possible to DP pin GPIO directly connected to connector Description USB power control pin USB power pin Negative differential data line
DP
Positive differential data line
USB_ID
USB identification pin. Pull-up on GPIO pin must be enabled
9.5 USB DFU ISP entry point
The ISP is activated according to the boot process conditions described in the boot loader document (see section 3.4). By default, the hardware condition is to maintain pin PA14 of UC3 C at logical 0 while releasing the reset. Once the ISP is activated, it establishes a USB connection with the connected PC. This I/O should not be used by the application if the USB DFU boot loader is required to program the application.
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10 Ethernet interface
When designing in the Ethernet physical device (PHY), the designer should refer to the datasheet for the PHY. This datasheet usually contains layout advice, connection schematics, reference design, etc. The information in the PHY datasheet is mandatory to get optimal performance and stability.
10.1 Ethernet interface in MII mode
Figure 10-1. Ethernet interface in MII mode example schematic.
Table 10-1. Ethernet interface in MII mode checklist.
Signal name TX_CLK/ REF_CLK CRS COL MDIO MDC RX_DV RXD[0:3] Recommended pin connection Description Transmit clock, 25MHz for 100Mb/s data rate Carrier sense Collision detect PHY maintenance data PHY maintenance clock Receive data valid Receive data 4-bit
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Signal name RX_ER RX_CLK TX_EN TXD[0:3] TX_ER Recommended pin connection Description Receive error Receive clock, 25MHz for 100Mb/s data rate Transmit enable Transmit data 4-bit Transmit error
10.2 Ethernet interface in RMII mode
Figure 10-2. Ethernet interface in RMII mode example schematic.
TX_CLK/REF_CLK
CRS
COL Ethernet PHY X1 MDIO MDC CRS RX[0:1] RX_ER TX_EN TX[0:1] RXD[0:3] RX_DV MDIO
MDC
RX_ER
RX_CLK
TX_EN
TXD[0:3]
TX_ER
Table 10-2. Ethernet interface in RMII mode checklist.
Signal name TX_CLK/ REF_CLK CRS COL MDIO MDC RX_DV Not used in RMII mode Not used in RMII mode PHY maintenance data PHY maintenance clock Carrier sense, data valid Recommended pin connection Description Reference clock, 50MHz for 100Mb/s data rate
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Signal name RXD[0:1] RXD[2:3] RX_ER RX_CLK TX_EN TXD[0:1] TXD[2:3] TX_ER
Recommended pin connection Not used in RMII mode
Description Receive data 2-bit Receive error
Not used in RMII mode Transmit enable Transmit data 2-bit Not used in RMII mode Not used in RMII mode
10.3 Ethernet Wake-on-LAN
The MACB controller supports Ethernet Wake-on-LAN (WOL), which can be used to wake the UC3 C core on network activity. Figure 10-3 shows an example of how the WOL output signal can be routed to an external interrupt input. Figure 10-3. MACB WOL to external interrupt example schematic.
Table 10-3. MACB WOL connection checklist.
Signal name MACB - WOL EIC - EXTINT Recommended pin connection Description MACB Wake-on-LAN output EIC external interrupt input
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11 External bus interface
11.1 Static memory
11.1.1 16-bit static memory Table 11-1. 16-bit static memory pin wiring.
GPIO line name EBI-DATA[0:15] EBI-ADDR[1:23] EBI-ADDR[0] (NBS0) EBI-NWE1 (NBS1) EBI-NWE0 EBI-NRD EBI-NWAIT EBI-NCSx 16-bit static memory D[0:15] A[0:22] LBE HBE WE OE WAIT CS
11.1.2 8-bit static memory Table 11-2. 8-bit static memory pin wiring.
GPIO line name EBI-D[0:7] EBI-A[0:23] EBI-NWE0 EBI-NRD EBI-NWAIT EBI-NCSx 8-bit static memory D[0:7] A[0:23] WE OE WAIT CS
11.1.3 2 x 8-bit static memory Table 11-3. 2 x 8-bit static memory pin wiring.
GPIO line name EBI-D[0:7] EBI-D[8:15] EBI-A[1:23] EBI-NWE0 (NBS0) EBI-NWE1 (NBS1) EBI-NRD EBI-NWAIT EBI-NCSx OE WAIT CS A[0:22] WE WE OE WAIT CS 8-bit static memory D[0:7] D[0:7] A[0:22] 8-bit static memory
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11.2 SDRAM
11.2.1 16-bit SDRAM Table 11-4. 16-bit SDRAM pin wiring.
GPIO line name EBI-D[0:15] EBI-A[2:11] EBI-SDA10 EBI-A[13:14] EBI-A[16] (BA0) EBI-A[17] (BA1) EBI-SDCK EBI-SDCKE EBI-SDWE EBI-RAS EBI-CAS EBI-A[0] (NBS0) EBI-NWE1 (NBS1) EBI-NCS[1] (SDCS) 16-bit SDRAM DQ[0:15] A[0:9] A[10] A[11:12] BA0 BA1 CLK CKE WE RAS CAS DQML DQMH CS
11.2.2 2 x 8-bit SDRAM Table 11-5. 2 x 8-bit SDRAM pin wiring.
GPIO line name EBI-D[0:7] EBI-D[7:15] EBI-A[2:11] EBI-SDA10 EBI-A[13:14] EBI-A[16] (BA0) EBI-A[17] (BA1) EBI-SDCK EBI-SDCKE EBI-SDWE EBI-RAS EBI-CAS EBI-A[0] (NBS0) EBI-NWE1 (NBS1) EBI-NCS[1] (SDCS) CS A[0:9] A[10] A[11:12] BA0 BA1 CLK CKE WE RAS CAS DQM DQM CS 8-bit SDRAM DQ[0:7] DQ[0:7] A[0:9] A[10] A[11:12] BA0 BA1 CLK CKE WE RAS CAS 8-bit SDRAM
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11.2.3 4 x 4-bit SDRAM Table 11-6. 4 x 4-bit SDRAM pin wiring.
GPIO line name EBI-D[0:3] EBI-D[4:7] EBI-D[8:11] EBI-D[12:15] EBI-A[2:11] EBI-SDA10 EBI-A[13:14] EBI-A[16] (BA0) EBI-A[17] (BA1) EBI-SDCK EBI-SDCKE EBI-SDWE EBI-RAS EBI-CAS A[0] (NBS0) EBI-NWE1 (NBS1) EBI-NCS[1] (SDCS) CS CS A[0:9] A[10] A[11:12] BA0 BA1 CLK CKE WE RAS CAS DQM A[0:9] A[10] A[11:12] BA0 BA1 CLK CKE WE RAS CAS DQM DQM CS DQM CS A[0:9] A[10] A[11:12] BA0 BA1 CLK CKE WE RAS CAS 4-bit SDRAM DQ[0:3] DQ[0:3] DQ[0:3] DQ[0:3] A[0:9] A[10] A[11:12] BA0 BA1 CLK CKE WE RAS CAS 4-bit SDRAM 4-bit SDRAM 4-bit SDRAM
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12 Quadrature decoder
Depending on the quadrature encoder used, pull-up resistors may or may not be needed. Figure 12-1 shows an example of how the quadrature decoder (QDEC) can be connected to a quadrature encoder using pull-up on the signal wires. Figure 12-1. Quadrature decoder example schematic.
VDD
VCC
10 k
QEPA
A
10 k
B
10 k
QEPB
I GND
QEPI
Optional resistors Table 12-1. Quadrature decoder connection checklist.
Signal name QEPA QEPB QEPI Note: Recommended pin connection Quadrature encoder output A, 10k (1) pull-up Quadrature encoder output B, 10k (1) pull-up Quadrature encoder index output, 10k (1) pull-up Description Quadrature phase signal A digital input Quadrature phase signal B digital input Quadrature index signal digital input
1. These values are given only as a typical example
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13 CAN interface
The UC3 C embeds a CAN controller, which generates and handles digital transmission and reception signals TXD and RXD. These signals can be used to interface a CAN line driver, which generates the physical differential signals on the CAN bus. Figure 13-1 shows an example schematic using the Atmel AT6660 highspeed CAN transceiver. Usage of the CAN interface is detailed in the application note, AVR32129: Using the 32-bit AVR UC3 CANIF. Figure 13-1. CAN interface to AT6660 example schematic.
Table 13-1. CAN interface connection checklist.
Signal name TXLINE RXLINE Recommended pin connection Directly to connector pin Directly to connector pin Description Transmission line (output) Reception line (input)
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14 JTAG and Nexus debug ports
14.1 JTAG port interface
Figure 14-1. JTAG port interface example schematic. TMS
1 3 5 7 9
TCK TDO TMS EVTO TDI
2x5 header
GND VCC RESET
2 4
6 8
TDO VDD TCK 100 nF RESET
GND
10
TDI
Table 14-1. JTAG port interface checklist.
Signal name TMS TDO TCK RESET TDI EVTO Recommended pin connection Description Test mode select, sampled on rising TCK Test data output, driven on falling TCK Test clock, fully asynchronous to system clock frequency Device external reset line Test data input, sampled on rising TCK Event output, not used
14.2 Nexus port interface
Do not use any capacitors on NEXUS lines because they can cause a speed limitation. NEXUS uses GPIO multiplexed lines, and these should be dedicated for NEXUS when used.
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Figure 14-2. Nexus port interface example schematic.
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Table 14-2. Nexus port interface checklist.
Signal name TDI TMS TCK TDO RESET EVTI MDO[0:5] EVTO MCK0 MSE[0:1] Recommended pin connection Description Test data input, sampled on rising TCK Test mode select, sampled on rising TCK Test clock, fully asynchronous to system clock frequency Test data output, driven on falling TCK Device external reset line Event input Trace data output Event output Trace data output clock Trace frame control
14.3 aWire port interface
aWire is a single-wire debug solution that offers memory access, programming capabilities, and On-Chip Debug access. aWire can also be used as a UART when it is not used for debugging. A full-duplex mode can be used to increase speed, in which case data is transmitted on a second pin, DATAOUT. aWire uses the RESET_N pin for data in/data out. When using aWire, the board reset circuitry must be disconnected. Refer to Figure 14-3 which demonstrates the use of RESET_N for half-duplex mode, and Figure 14-4, where DATAOUT is added for fullduplex communication. Figure 14-3. Disconnecting the reset circuitry to allow aWire use. aWire DATA VDDIO 10 k 100 nF RESET_N
Figure 14-4. aWire with full-duplex communication.
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Table 14-3. aWire port interface checklist.
Signal name Recommended pin connection aWire in/out (half-duplex) aWire in (full-duplex) Disconnect from reset circuitry aWire out (full-duplex mode only) Description
RESET_N DATAOUT
Input/output Output
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15 Table of Contents
Features ............................................................................................... 1 1 Introduction ...................................................................................... 1 2 Abbreviations ................................................................................... 2 3 References........................................................................................ 2
3.1 Device datasheet................................................................................................. 2 3.2 The AVR Software Framework............................................................................ 2 3.3 The AT32UC3C-EK Getting Started ................................................................... 2 3.4 USB DFU boot loader.......................................................................................... 2
4 Power circuit .................................................................................... 3
4.1 Single 3.3V power supply.................................................................................... 3 4.2 Single 5V power supply....................................................................................... 5
5 Reset circuit ..................................................................................... 7 6 Clocks and crystal oscillators ........................................................ 8
6.1 External clock source .......................................................................................... 8 6.2 Crystal oscillator .................................................................................................. 8
7 ADC Analog-to-digital converter .................................................... 9
7.1 ADC analog Input ................................................................................................ 9 7.2 ADC voltage reference ........................................................................................ 9
7.2.1 ADC single-ended external reference (ADCREF0/ADCREF1).................................. 9 7.2.2 ADC differential external reference pins (ADCVREFP/ADCVREFN) ...................... 10
8 Digital-to-analog converter ........................................................... 12
8.1 DAC connection................................................................................................. 12
9 USB connection ............................................................................. 13
9.1 Not used ............................................................................................................ 13 9.2 Device mode, bus-powered connection ............................................................ 13 9.3 Device mode, self-powered connection ............................................................ 14 9.4 Host mode, powered from bus connection........................................................ 15 9.5 USB DFU ISP entry point .................................................................................. 15
10 Ethernet interface ........................................................................ 16
10.1 Ethernet interface in MII mode ........................................................................ 16 10.2 Ethernet interface in RMII mode...................................................................... 17 10.3 Ethernet Wake-on-LAN ................................................................................... 18
11 External bus interface ................................................................. 19
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11.1 Static memory.................................................................................................. 19
11.1.1 16-bit static memory .............................................................................................. 19 11.1.2 8-bit static memory ................................................................................................ 19 11.1.3 2 x 8-bit static memory .......................................................................................... 19
11.2 SDRAM............................................................................................................ 20
11.2.1 16-bit SDRAM ....................................................................................................... 20 11.2.2 2 x 8-bit SDRAM.................................................................................................... 20 11.2.3 4 x 4-bit SDRAM.................................................................................................... 21
12 Quadrature decoder..................................................................... 22 13 CAN interface ............................................................................... 23 14 JTAG and Nexus debug ports..................................................... 24
14.1 JTAG port interface ......................................................................................... 24 14.2 Nexus port interface ........................................................................................ 24 14.3 aWire port interface ......................................................................................... 26
15 Table of Contents......................................................................... 28
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